The present invention generally relates to a method for forming a mask pattern for ion-implantation. More specifically, the disclosure relates to a method comprising forming a coating film having a lower interfacial tension than that of a photoresist on the surface of a gate line pattern and forming a photoresist mask pattern for ion-implantation thereon to perform a subsequent ion-implanting process stably.
As the fields of application of memory devices have been extended, a manufacturing technology of semiconductor device has been urgently requested to manufacture a memory device of high capacity with improved integrity and without degradation of electric characteristics. As a result, a multilateral research to improve a photolithography processes, cell structures, and physical property limits of materials which form wires and insulating films have been made.
Meanwhile, an ion-implanting process is essentially applied to form the memory devices having electric characteristics, stably performing the ion-implanting process improves the final yield of semiconductor devices.
FIGS. 1a through 1d are diagrams illustrating a conventional method for performing ion-implantation process.
Referring to FIG. 1a, a gate material layer (not shown) is formed over a semiconductor substrate 1 including an isolation film (not shown) and then a photolithography and etch process is sequentially performed on the resulting structure to form a gate line pattern 3.
A photoresist layer 5 is formed on the resulting structure including the gate line pattern 3, as shown in FIG. 1b, so as to fill the gate line pattern 3 of FIG. 1a.
Thereafter, an exposure and developing process are performed on the photoresist layer 5 of FIG. 1b with an exposure mask for ion-implantation to form a photoresist pattern 5-1 as shown in FIG. 1c. A bit-line contact (BLC) node region 11 where a ion-implanting region is to be formed is opened at a predetermined width(a) and a storage node contact (SNC) node region 13 where a ion-implanting region is not to be formed is filled at a predetermined height(b) so that the photoresist pattern 5-1 may be used as a mask for ion-implantation in a subsequent ion-implanting process.
Then, the ion-implanting process 7 is performed with the photoresist pattern 5-1 as a mask pattern for ion-implantation (see FIG. 1d).
However, the conventional method for performing ion-implantation process has the following problems.
Since the aspect ratio of the gate line pattern increases by decreasing a pattern critical dimension (hereinafter, referred to as “CD”) of a semiconductor device, the lower part of the gate line pattern is not sufficiently exposed to an light source during the exposure process. As a result, a photoresist material 9 remains in the BLC node region 11 as shown in FIG. 1c even after the developing process is completed. Moreover, when the gate line pattern is non-uniformly filled using the photoresist material, voids (not shown) are generated.
In order to remove the residual photoresist material, a descum process which is an etch-back process is performed on the final resulting structure, and the width size (a′) of the upper part of the photoresist pattern of the BLC node region 11 is enlarged and the height (b′) of the photoresist pattern of the SNC node region 13 is reduced as shown in FIG. 1d. As a result, since the photoresist pattern of the SNC node region 13 does not have the enough thickness to serve as a barrier in the subsequent ion-implanting process as shown in FIG. 1d, even a region having no ion-implanting region is damaged during the ion-implanting process.
When an ultra-fine pattern having a high aspect ratio is formed with an exposer having a high lens numerical aperture (hereinafter, referred to as “NA”), the damage is more severe, thereby reducing the manufacture yield of the final semiconductor device.